Page 683 - Engineering Digital Design

13.6 SYSTEM-LEVEL DESIGN 651

to be only a "thinking tool" for the construction of the state diagram or state table from
which the controller is designed.
There may be more than one good design for a given digital system. This is particularly
true for complex digital systems. The success of the design will usually depend on the
engineering creativity, intuition, and generally the experience of the digital designer. But
the manner in which a digital system is to operate in a particular environment can also be an
important factor. For example, suppose a stepping motor control system is to be designed
to move a certain mass from one fixed position to another in a smooth, nonjerky fashion.
Clearly, the design considerations for the stepping motor controller, based on mass, time,
and distance constraints, are different for the operation of a small robotic arm than for the
operation of an elevator. The point is that important detailed information regarding timing
and functional constraints must be factored into the design process from the beginning
stages if successful designs are to result.

13.6.1 Design of a Parallel-to-Serial Adder/Subtracter Control System

A brief description of the parallel-to-serial adder/subtractor system was given in Subsection
13.5.3. There, the one-hot-plus-zero approach was used to design the system controller
shown in Figs. 13.31 and 13.32. Now, it is necessary to construct the functional partition for
this system. This is done in Fig. 13.34, where block circuit symbols are used to represent the
controller and data path devices. The data path unit (DPU) consists of two 8-bit USRs, a full
adder (FA), an RET D flip-flop, a controlled inverter (XOR gate), and a 4-bit parallel loadable
up/down counter of the type shown in Fig. 12.20. Of course, there are many "variations
on the theme" in the design of the DPU. For example, right shift registers with parallel
load capability can replace the USRs, a simple 3-bit binary up counter with asynchronous
CL can replace the 4-bit parallel loadable up/down counter, and a transparent D latch with
asynchronous PR and CL overrides (Fig. 10.51) can replace the edge-triggered D flip-flop.
If operands larger than 8-bits are to be added or subtracted, larger registers must be used.
Thus, two 8-bit registers can be cascaded in series to accommodate 16-bit operands, or four
8-bit registers can be cascaded to accommodate 32-bit operands, etc.
Presented in Fig. 13.35a is a reconstruction of the state diagram for the parallel-to-serial
adder/subtractor controller in Fig. 13.3la, but now with a state code assignment suitable
for a conventional design. In Fig. 13.35b is shown the timing diagram for an 8-bit serial
subtraction operation by the adder/subtractor system. Notice that the sequence of events
indicated in the timing diagram are the same as those in the state diagram and that they,
together with the functional partition in Fig. 13.34, provide a complete stepwise description
of this system: Following initialization of the adder/subtractor in state a, the controller
loads a 0000 into the counter and clears the USRs. After the start button Start is pressed
(for a period of time greater than a clock period) the controller transits from state a to state
b. In state b the RET D flip-flop and mode control S\ are set to logic 1 by the controller
in preparation for subtraction. The carry-in CI to the FA is now initialized to logic 1, as
required for subtraction by 2's complement. After the release of the Start switch button
(hence Start), the controller transits to state c, where counting by the counter is begun.
During this time, the two 8-bit USRs deliver the operands serially LSB first to the full
adder (FA) via a controlled inverter on the B line, which is now set to complement B
[CMPL(H) = !(//)] as required for subtraction. With each clock triggering edge, bitwise