Page 681 - Engineering Digital Design

13.6 SYSTEM-LEVEL DESIGN 649

requires a macrocell and if each Mealy output must also use a macrocell, the capability of the
PAL can be quickly used up for all but relatively small FSMs. Therefore, as a rule, it is best
to use registered PAL devices for one-hot designs of relatively small FSMs with only Moore
outputs. Used in this manner, registered PAL designs by the one-hot method offer quick,
convenient and reliable results, and without the need for K-maps or programming soft-
ware. See subsection 16.4.4 for information regarding synchronous one-hot programmable
sequencers.
If registered PLDs are to be used to implement large Mealy state machines by the one-hot
method, FPGAs are the best choice. A good example is the use of the 4000 series Xilinx
FPGAs. As explained in Subsection 7.7.3, these devices are extremely versatile and have
the capacity to handle very large one-hot state machine designs with both Moore and Mealy
outputs. The one drawback in the use of these FPGAs is that they require dedicated soft-
ware to program them. For all but the experienced user of Xilinx FPGAs, this requirement
is an impediment to design and may even preclude their use. Xilinx FPGAs accept VHDL
descriptions of state machines from which the FSM can be synthesized automatically by
synthesis tools such as AutoLogic VHDL by Mentor Graphics. For more information on
these subjects see references cited in Further Reading at the end of this chapter.
There still remains the question of initializing registered PLDs for one-hot designs.
R-type PAL devices apparently lack initialization capability and are not recommended for
use in most one-hot designs. The macrocells of V-type PAL devices contain D flip-flops
with both PRE and CLR asynchronous overrides. Thus, V-type PALs can be initialized
directly into a one-hot state but are otherwise limited in their use in one-hot applications
as explained earlier. The configurable logic blocks (CLBs) of all Xlinx FPGAs contain D
flip-flops with both PRE and CLR overrides and consequently are suitable for one-hot state
initialization. Generally, registered PLDs having D flip-flops with only CLR overrides can
be used, but only for the one-hot-plus-zero approach as indicated by previous examples.
Finally, there is software called A-OPS (for Asynchronous-One-hot Programmable Se-
quencers) on the CD-ROM bundled with this text that can be used to automate the design
of PLA or RAM driven asynchronous and synchronous one-hot state machines. Initializa-
tion into the all zero state is possible by using the one-hot-plus-zero approach. For more
information regarding this software, refer to Appendix B.

13.6 SYSTEM-LEVEL DESIGN: CONTROLLER, DATA PATH,
AND FUNCTIONAL PARTITION

One very common view of a digital system is the use of an FSM as the controller for a set
of components parts that comprise the controlled system called the data path. This view
is expressed in Fig. 13.33, where all input and output (I/O) conditioning logic has been
omitted to focus attention on the main features of this architecture. Here, it is understood
that the data path devices generally consist of a mixture of both sequential and combinational
logic machines. Typical among these are registers, counters, ALUs, PLDs of various types,
decoders, MUXs, shifters, comparators, digital-to-analog (D/A) converters, and the like.
The architecture represented in Figure 13.33 is the one emphasized in this text.
All sections in this chapter up to this point have been devoted to various architectures
that can and should be considered in controller design. Chapters 10, 11, and 12 supply
the necessary background information needed to build reliable controllers as well as those