Page 702 - Engineering Digital Design

668 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES

considerable knowledge of the use and interpretation of this software is needed before
reliable designs can result. But even with that knowledge, the designer must still deal
with a variety of timing problems. In some system-level designs timing is everything and
improper routing delays can cause malfunction of the system. Fortionately, Xilinx Corp.
has taken this into account and has provided generous routing resources in their XC4000E
and XC4000XV series FPGAs and have made them reprogrammable an unlimited number
of times. The section on Futher Reading at the end of this chapter cites relevant sources of
information on this subject.
If it is the designer's intent to use a so-called programmable logic sequencer (PLS) for
total system design, be aware of the limitations of such a device. Although many of these
devices conform to the model in Fig. 13.47, the number of flip-flops they provide may be
quite limiting. For example, the Signetics PLS155 provides the equivalent of a 16 x 45 x 12
PLA but is equipped with only four edge-triggered flip-flops on chip. Of course, such devices
can be combined to accommodate larger designs, but compared to what FPGAs can offer, it
may not seem worthwhile. This is not to say that individual PLSs cannot be useful in simple
controller designs. Even the Signetics PLS 155 can be useful in the design of FSMs having
four or fewer state variables. Remember that FSMs up to 16 states can be designed by using
four flip-flops as the memory. But for very large controller- and system-level designs, it is
advisable to look elsewhere for a suitable PLD. In particular, FPGAs should be considered
as the ideal choice for such FSMs provided that the appropriate software is available for
programming.

FURTHER READING

To one extent or another, every text on digital design contributes something to the subject
of alternative architectures in synchronous controller design and, perhaps to a lesser extent,
to system-level design. Useful sources for further reading on the subject of alternative
controller designs of state machines can best be found in texts by Fletcher and Tinder, and
to a lesser extent in the texts by Katz and Roth. The texts by Fletcher and Tinder provide
extensive coverage of counter- and register-based controller design. The use of MUXs and
state decoders is also covered in these two references.

[1] W. I. Fletcher, An Engineering Approach to Digital Design. Prentice Hall, Englewood Cliffs,
NJ, 1980.
[2] R. H. Katz, Contemporary Logic Design. Benjamin/Cummings Publishing, Redwood City, CA,
1994.
[3] C. H. Roth, Fundamentals of Logic Design, 4th ed. West Publishing Co., St. Paul, MN, 1992.
[4] R. F. Tinder, Digital Engineering Design: A Modern Approach, Prentice Hall, Englewood Cliffs,
NJ, 1991.

Further reading on the subject of controller design centered around nonregistered PLDs,
mainly ROMs and PLAs, can be found in the four previously cited references. In addition,
the text of Nelson et al. provides useful further reading on this subject.

[5] V. P. Nelson, H. T. Nagle, B. D. Carroll, and J. D. Irwin, Digital Logic Circuit Analysis and
Design. Prentice Hall, Englewood Cliffs, NJ, 1995.