Page 705 - Engineering Digital Design

PROBLEMS 671

flip-flop (NAND-based or NOR-based) that should be used. Remember that a
PLA is an SOP device.
(b) By using third-order K-maps, obtain an optimal set of expressions for the NS
functions.
(c) Construct the p-term table and block diagram for an FPLA design of this FSM.
To do this, use a 5 x 13 x 5 FPLA (as a block symbol) to design an optimum
glitch-free logic circuit for this FSM. Plan to filter the output signals only if nec-
essary. Do not alter the state diagram. Assume that input X is asynchronous from
a mechanical switch (switch Down in Fig. 11.32a is the active state), that input Y
is synchronous, and that both arrive active low. Take the outputs as active high.

13.2 A counter is to be designed that will drive the seven-segment display in Fig. 6.22a
directly from its seven state variables, that is, from the flip-flop outputs, A, B, C,
D, E, F, and G. When the counter is connected to the common cathode LED array
in Fig. 6.23b, seven-segment Arabic numerals will appear. The FSM must have a
count-up enable control X and must be cascadable so that numerals greater than 9
can be displayed. Thus, two such counters in cascade will count with each clock
cycle, • • • 0-1-2-3 90-0- • •, but only if enabled.
(a) Construct the state diagram for this FSM. Plan to initialize it into the decimal
zero state.
(b) Assuming the use of D flip-flops, map the state diagram directly into seven
fourth-order EV K-maps and extract minimum or near minimum cover for
each of the seven NS functions by using a logic minimizer such as BOOZER.
(Suggestions: The simplest approach is to use the map format AB/CD \ \ E/FG
by following the example in Fig. 5.7 as an array of third-order K-maps. Each
cell of a given fourth-order NS K-map will represent a third-order submap with
axes E/FG and one entered variable, X. Thus, each NS K-map represents a
fourth-order compression. It will be helpful to divide each state code assignment
of the state diagram into two parts, the most significant four bits for the K-map
axes AB/CD and the least significant three bits for the submaps. Note that the
use of submaps is necessary only for cells 6, 14 and 15.)
(c) Use an 8 x 32 x 8 FPLA to implement the NS- and output-forming logic.
Assume that the inputs and outputs are active high. To do this, construct the
p-term table and block diagram for this FSM.
13.3 The state diagram in Fig. P13.2a represents the controller for a candy-bar vending
machine. The controller has six inputs and four outputs, all of which are defined in
Fig. P13.2b.
(a) Construct a minimum size p-term table for implementation of the NS and output
functions by using an FPLA. To do this, assume that D flip-flops are to be used as
the memory, and note that only one of the inputs LT, GT, or EQ can be active at
any given time — they are the outputs from a comparator. Furthermore, assume
that all inputs and outputs are active high.
(b) From the results of part (a), construct the logic circuit for the vending machine
controller. Plan to use RET D flip-flops and to initialize into the 000 state. If
ORGs are present, take the necessary steps to eliminate them, but do not change
the state code assignment that is given. Use a block symbol for the PLA and