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14.12 SINGLE-TRANSITION-TIME MACHINES                                727



                    Collectively, the NS and output functions generated from the array algebraic approach
                 are

                                    F 3 = yiS + yiST + y^yiST + y 0ST
                                              +y 2T

                                                                                   (14.34)
                                    FO = ST + y 2ST + yoS




                 which represents a gate/input tally of 14/40 taking into account four shared Pis and excluding
                 possible inverters. Notice that all five output p-terms are covered by p-terms in the NS logic
                 functions owing to the four shared Pis. This is characteristic of the array algebraic approach
                                                                     1
                 to FSM design since the same form of the function matrix F = Z D is used for the output
                 functions as for the NS functions.
                    The NS and output functions in Eqs. (14.34) are guaranteed to be free of critical races
                 and ORGs. This is a result of using the array algebraic approach on the state assignment
                 matrix of Eq. (14.29), the combination of which is inherently exclusionary of all race related
                 problems. However, the result is not expected to be an optimal result. The array algebraic
                 approach to FSM design used in this section is attractive from another point of view: It
                 offers a method for obtaining the NS and output functions of STT state machines that is
                 amenable to computer aided design (CAD).
                    Logic minimization methods should rarely, if ever, be used to obtain the NS and output
                 functions directly from the state diagrams of STT state machines. The reason is that an STT
                 state code assignment is, by itself, not sufficient to ensure a critical race-free and ORG-free
                 design. For example, if an optimal K-map minimization approach is used directly on the
                 state diagram in Fig. 14.33a with the STT state code assignments given by Eq. (14.29), a
                 result is obtained that cannot be guaranteed to be free of critical races and ORGs. The NS
                 and output functions must be "looped out" correctly to avoid race-related problems — a
                 task performed automatically by the array algebraic approach.
                    There remains the question of static hazards in Eqs. (14.34). A static hazard analysis of
                 Eqs. (14.34) indicates that there are seven active static 1-hazards in the NS functions, three
                 in function F 3, one in Y 2, and three in function Y 0, but all are externally activated. Shown
                 in Eqs. (14.35) are the NS functions with hazard cover included for these seven s-hazards.
                 Also shown is the hazard cover for the singular externally initiated static 1-hazard in the
                 output Q. When this hazard cover is included, the gate/input tally for Eqs. (14.35) becomes
                 21/68. However, there is one potentially active static 1-hazard in function Y\ if a delay
                 greater than that of an inverter is placed on the noninverter path, that is, on the T line to
                 gate y\ST. There are also two such potentially active s-hazards in output function Q, one
                 between coupled terms y^ST,y\ST and the other between coupled terms y^ST, yoST. In
                 each of these latter two cases an s-hazard could form if a delay exceeding that of an inverter
                 is positioned on the noninverter line of the coupled variable to the coupled term gate. The
                 hazard covers for these hazards are not shown in Eqs. (14.35) since they are not likely to
                 form, although some designers may include them to ensure proper operation of the FSM.
                 The term "potentially active" applies to any hazard that must be activated by an unintended
                 delay that is explicitly located along some path in the circuit — a delay that cannot always
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