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98    Cha pte r  T h ree


                    smoother surface. It should be noted that both coarser and fine background wafers
                    produce wafer warpage because of the damaged layer created during the back-grinding
                    process. This damage also becomes a source of cracks that propagate subsequently
                    when the chips are stressed.
                       The next step after grinding is polishing, which is required to remove or reduce the
                    damage produced by fine grinding, leading to enhancement of wafer strength and
                    wafer warpage. Several polishing methods have been employed, which include
                    chemical and mechanical polishing (CMP), dry and wet polishing, and dry (downstream
                    plasma) and wet etching.

                           Chemical and mechanical polishing (CMP) [13]. CMP uses a special pad with slurry
                           containing ammonium hydroxide to simultaneously chemically etch and
                           mechanically remove silicon. This synergy between chemical and mechanical
                           processes in the CMP process reduces the mechanical forces required for
                           polishing. The CMP removes most of the damage caused during coarse and
                           fine grinding, restoring both the mechanical strength and wafer bow to their
                           original status, while giving wafers a mirror finish.
                           Dry polish. Dry polishing uses an abrasive pad without any chemicals, as the
                           name suggests. Wafers that undergo stress relief through dry polish are expected
                           to have higher die strength, lower surface roughness, and lower wafer warpage
                           compared to those undergoing the grinding process only.
                           Wet polish [14]. Wet polish is a well-developed process used to remove silicon
                           wafer. It uses slurry, composed of SiO  and water (around 40 to 50 wt% of SiO ).
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                           Silica particle sizes range from 5 to 100 nm, with an average size of about 30 to
                           50 nm. This process mechanism is similar to CMP with a lower capital investment
                           and a lower processing cost but with a lower throughput, however.
                           Dry etching (downstream plasma) [15]. Microwave-excited plasma reacts with the
                           silicon wafer surface to chemically remove silicon. The tool uses a mixture of
                           SF  and oxygen gases. Silicon is removed by the chemical reaction: Si + 4F →
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                           SiF . The oxygen in the gas mix removes the reaction products. Such a
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                           downstream plasma process reduces wafer heating to below the 90°C,
                           preventing face tape burn. It also produces a significantly higher silicon removal
                           rate, as compared to wet etching. This process is contactless and does not
                           require protective tape to be applied to the wafer topside, which reduces the
                           associated processing costs and allows for processing of bumped wafers.
                           Wet etching. Wet etching can be applied, provided that wafers remain relatively
                           thick to withstand physical handling. Such etchants as HF and HNO  are typically
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                           included in spite of process control difficulties that limit the wet-etch processes.

                    Thin-Wafer Handling  Secure handling and processing of very thin wafers are generally
                    accomplished by temporarily bonding a rigid carrier onto the wafer front side before
                    thinning. Well-known techniques use polymeric bonding agents like wax, thermally
                    releasable adhesive tapes, or dissolvable glues [16]. Although wax bonding is commonly
                    used, it is a time-consuming process and needs specific cleaning procedures to remove
                    residuals of the bonding layer.  Application of thermal release tapes has become a
                    widespread method in order to support wafers with low topographies during thinning
                    processes. A carrier is attached to the wafer to be processed by means of a double-sided
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