Page 254 - System on Package_ Miniaturization of the Entire System

228 Cha pte r F o u r

One possible solution is to provide on-chip decoupling above 100 MHz. Previous
work has illustrated the effect of on-chip capacitance for decoupling switching circuits
[73–76]. The main disadvantage with this approach is the low capacitance value associated
with on-die capacitance. This renders them effective at frequencies much above 100 MHz.
The amount of on-die capacitance can be increased, but this would compromise the
amount of real estate available for including logic circuits. Another approach investigated
in [77–81] is to include planar embedded capacitors within a board or package. In this
approach, the capacitor is assumed to be a thin dielectric layer within the package or the
board. Another innovative method presented in [82] uses a capacitance interposer
between the chip and the board to provide decoupling for the switching circuits.
A very promising method for decoupling is the use of discrete thick- or thin-film
capacitors arranged in a capacitive array that can be used within a package to provide
decoupling for high-performance circuits in the frequency range from 100 MHz to 2 GHz.
Using an array of capacitors allows for control of the resonant behavior of each capacitor
for broadband decoupling.

4.7.1 Need for Decoupling in Digital Applications
The power densities of microprocessors have grown over the years due to the increase
in the number of transistors and the increase in the processor operating frequency. The
major contributors to the power dissipation in the sub-100-nm technology nodes are the
active and static power dissipation.
The active power dissipation of a processor is given by [83]

P = α CV 2 f
active core (4.29)
where Vcore is the core voltage of the processor, a is the activation factor of the processor,
C is the capacitance that is switched in each clock cycle, and f is the frequency of
operation of the processor. The static power dissipation of the processor is given by

P static = V core × I leakage (4.30)
where I leakage is the total leakage current of the processor.
The power dissipation of a processor can be calculated using the product of the
average current of a processor and the core voltage. The average power dissipation of a
processor is given by
P = V core × I avg (4.31)
The estimated power dissipated for the 65-nm node cost performance processor from
[85] is 103.6 W and V core is 0.9 V. Using Equation (4.31), the average current I drawn by
avg
the processor is 115.1 A. The target impedance for this processor is calculated by
substituting the value of V core and I in Equation (4.28). Table 4.11 lists the different
avg
parameter for processors in the 90-, 65-, and 45-nm nodes.
From the table it is evident that the target impedance is decreasing with an increase
in the technology nodes. As mentioned before, the methodology for meeting the target
impedance is to place decoupling capacitors in the PDN. The number and type of
decoupling capacitors required depends on the frequency band to be targeted and the
equivalent series resistance of each individual capacitor. The number of capacitors of
each type can be decided by the ESR of each type of capacitor and the target impedance
to be met given by
N = target impedance / ESR (4.32)
cap cap