Page 35 - System on Package_ Miniaturization of the Entire System

Intr oduction to the System-on-Package (SOP) Technology 13

components required to form a complete end-product system), then all that is necessary
to package such a system is to provide protection, external connections, power, and
cooling. If this can be realized, SOC offers the promise for the highest performance
and the most compact, lightweight system that can be mass-produced. This has been
and continues to be the road map [8] of IC companies.
So the key question is whether SOC can lead to cost-effective, complete end-product
systems such as tomorrow’s leading-edge cell phones with digital, wireless, and sensing
capabilities or biomedical implants. Researchers around the world, while making great
progress, are realizing that SOC, in the long run, presents fundamental limits for computing
and integration limits for wireless communications and additional nonincremental costs to
both. Among SOC challenges are the long design times due to integration complexities,
high wafer fabrication costs and test costs, and mixed-signal processing complexities
requiring dozens of mask steps and intellectual property issues. The high costs are due to
the need to integrate active but disparate devices such as bipolar, CMOS, silicon germanium
(SiGe), and optoelectronic ICs—all in one chip with multiple voltage levels and dozens of
mask steps to provide digital, RF, optical, and MEMS-based components.
It is becoming clear that SOC presents major technical, financial, business, and legal
challenges that are forcing industry and academic researchers to consider other options
for semiconductors and systems. For the first time, industry may not invest in extending
Moore’s law beyond 2015. This is leading the industry to explore alternative ways to
achieve systems integration wherein semiconductor integration is pursued, not only
horizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICs
and by SOP. More than 50 companies are pursuing SIP as indicated in Chapter 4.
Hence, a new paradigm that overcomes the shortcomings of both SOC and
traditional systems packaging is necessary. The SOP technology described in this book
makes a compelling case for the synergy between the IC and the package integration by
means of the SOP concept, which can also be applied to SOCs and SIPs, as well as to
silicon wafer, ceramic, or organic carrier platforms or boards.

1.5.3 Multichip Module (MCM): Package-Enabled Integration
of Two or More Chips Interconnected Horizontally
The MCM (Figure 1.6) was invented back in the 1980s at IBM, Fujitsu, NEC, and Hitachi for
the sole purpose of interconnecting dozens of good bare ICs to produce a substrate wafer
that looked like the original wafer, since larger chips could not be produced with any
acceptable yields on the original silicon wafer. These original MCMs were horizontal or two-
dimensional. They started with so-called high-temperature cofired ceramics (HTCCs)—
multilayer ceramics, such as alumina, metallized and interconnected with dozens of layers
of either cofired molybdenum or tungsten. These then were replaced with higher-performance
ceramic MCMs called low-temperature cofired ceramics (LTCCs)—made of lower-dielectric-
constant ceramics such as glass-ceramics, metallized with better electrical conductors such as
copper, gold, or silver-palladium. The third generation of MCMs improved further with
add-on multilayer organic dielectrics and conductors of much lower dielectric constant and
sputtered or electroplated copper with better electrical conductivity.

1.5.4 Stacked ICs and Packages (SIP): Package-Enabled IC Integration with
Two or More Chip Stacking (Moore’s Law in the Third Dimension)
Here, SIP is defined as a vertical stacking of similar or dissimilar ICs, in contrast to the
horizontal nature of SOC, which overcomes some of the above SOC limitations, such as