Page 36 - System on Package_ Miniaturization of the Entire System

14 Cha pte r O n e

latency, if the size of the chips and their thicknesses used in stacking are small. SIP is also
defined often as the entire system-in-a-package. If all the system components (for example,
passive components, interconnections, connectors, and thermal structures such as heat
sinks and thermal interface materials), power sources, and system board are miniaturized
and integrated into a complete system as described in this book as SOP, then there is no
difference between SIP and SOP. The intellectual property issues as well as yield losses
associated with dozens of sequential mask steps and large-area IC fabrication are also
minimal. Clearly, this is the semiconductor companies’ dream in the short term.
But there is one major issue with this approach. The SIP, defined above as stacking of
ICs, includes only the IC integration and hence addresses only about 10 to 20 percent of
the system by extending Moore’s law in the third dimension. If all the ICs in the stack are
limited to CMOS IC processing, the end-product system is limited by what it can achieve
only with CMOS processing at or below nanoscale. The above fundamental and integration
barriers of SOC, therefore, remain. There are clear major benefits, however, to SIP: simpler
design and design verification, a process with minimal mask steps, minimal time-to-
market, and minimal Intellectual Property (IP) issues. Because of the above-mentioned
SIP benefits, however limited, about 50 IC and packaging companies alike have geared
up in a big way to produce SIP-based modules (Figure 1.10).

SIP Categories
The SIP technology can be broadly classified, as shown in Figures 1.10 and 1.11, into two
categories: (1) stacking of bare or packaged ICs [9–12] by traditional wire-bond, TAB, or
flip-chip technologies, and (2) stacking by through-silicon vias (TSVs), without using
wire bond or flip chip. SIP and 3D packaging are often meant to be the same and are
loosely referred to as the vertical stacking of either bare or packaged dies. In this book,
however, 3D package integration refers to stacking of ICs by means of TSV technology.
SIP by Wire Bonding Three-dimensional integration of bare dies can be done using wire
bonding as shown in Figure 1.12. In this approach, the different stacked dies are
interconnected using a common interposer (or package). The individual dies are
connected to this interposer by wire bonds. Wire bonding is economical for interconnect
densities of up to 300 I/Os. However, it suffers from the high parasitic inductance of the
wire bonds. There is a lot of inductive coupling between the densely placed wire bonds
which results in poor signal integrity.

SIP by Flip Chip and Wire Bonding In this 3D integration technique, as shown in Figure 1.13,
the bottom die of the stack is connected to the package by flip-chip bonds. All other dies
on the top of it are connected to the package using wire bonds. This eliminates the wire
bonds required for the bottom die, but still suffers from the high parasitics of the wire
bonds for the upper dies.

SIP by Flip Chip–on–Chip The bare dies are flip-chip bonded with each other in this
approach of 3D integration as shown in Figure 1.14a and b. The dies are arranged face-
to-face with the Back End of Line (BEOL) areas of the dies facing each other. The bottom
die is usually bigger than the top die. The bottom die is connected to the package by
wire bonds.
3D Integration by Through-Silicon-via Technology Three-dimensional integration enables
the integration of highly complex systems more cost-efficiently. A high degree of