Page 46 - System on Package_ Miniaturization of the Entire System

Intr oduction to the System-on-Package (SOP) Technology 23

leading to nanometer nodes currently from micrometer nodes in the 1970s. This
miniaturization is expected to continue through at least 32 nm and perhaps beyond. The
miniaturization in IC packages, however, was not so dramatic. As can be seen from
Figure 1.18, the dual in-line packages with only I/Os in centimeter size in the 1970s
migrated to Quad-Flat Pack (QFP) with I/Os on all four sides of the package in the
1980s. Both are lead frame based, making them bulky. The next wave in miniaturization
led to solder ball attach and surface mount assembly to the board and was typically
achieved with ball grid arrays. The IC assembly miniaturization followed a similar path
starting with coarse-pitch peripheral wire bond, then finer pitch, and then to area array
wire bond by some companies. Further miniaturization at the IC level was brought about
by a major breakthrough by IBM, commonly referred to as “flip chip.” The flip-chip
miniaturization that started in the 1970s at the millimeter pitch, is paving the way to 10-
to 20-micron pitch by 2015. The so-called chip scale package that was no more than 20
percent larger in size than the packaged ICs was the next miniaturization technology
currently implemented at the wafer level. Further miniaturization has been accomplished
with bare chips by so-called chip-on-board or flip-chip MCM technologies.
The next wave in miniaturization has been achieved by 2D MCMs for ultrahigh
computing performance, as shown previously in Figure 1.5. Two factors contributed to
this miniaturization: (1) the highly integrated substrate and its multilayer fine line and
via wiring dimensions, and (2) 2D dimensions with as many as 144 bare chips
interconnected in 100- to 144-mm size substrate. The market need for cell phones
changed this 2D approach to 3D, achieved by stacking as many as 9 thinned chips to
date with the potential to stack 20 or more by 2015. Two major factors contributed to
this miniaturization: (1) thinned chips to 70 microns in thickness and (2) shorter and
finer-pitch flip-chip assemblies. The next paradigm in miniaturization is being achieved
by so-called through-silicon-via technology, as described above, and pad-to-pad
bonding, replacing the flip-chip assembly.
The fraction of the system miniaturized by the above IC-based and Moore’s law driven
technologies, as shown in Figure 1.22, is typically about 10 to 20 percent of the system,
leaving the remaining 80 percent in a bulky state. This 80 percent consists of such system
components as passives, power supplies, thermal structures, sealants, intersystem
interconnections, and sockets. This is what SOP is all about, miniaturizing these components
from their milliscale to microscale in the short term and nanoscale in the long term.

1.7 Comparison of the Five System Technologies
Figure 1.23a lists the system drivers as being miniaturization, electrical performance,
power usage, thermal performance, reliability, development and manufacturing cost,
time-to-market, and flexibility. Figure 1.23b compares each of the above system
technologies against the same parameters, showing the strengths and weaknesses of
each of the technologies.
The SOC is a clear technology leader in electrical performance and power usage,
and while it is a miniaturization leader at the IC level, it is not a leader at the system
level, as can be seen in Figure 1.23b. This is due to the fact that the system technologies
such as power supplies and thermal structures are not miniaturized. The high
development cost, longer time-to-market, and limited flexibility are its major weaknesses.
In addition, complete integration of RF, digital , and optical technologies on a single
chip poses numerous challenges. RF circuit performance, for example, is a tradeoff
between the quality factor (Q) of passive components (inductors and capacitors) and