Page 279 - Sami Franssila Introduction to Microfabrication

258 Introduction to Microfabrication

Polysilicon, thickness ca. 500 nm, is deposited undo- pattern, whereas the contact holes will be ca. 2 µm wider
ped.A separatePOCl 3 gas-phasedoping step is performed than the resist dimensions. Overlap rules must make
after deposition, and the resulting poly sheet resistance is sure that the metal covers the contact completely (Figure
ca. 30 ohm/sq. Both NMOS and PMOS gates are made of 25.2(i)). After stripping and wafer cleaning, forming gas
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the same material, the phosphorus-doped poly. anneal at 450 C improves silicon-to-aluminium contact.
The fourth photomask defines the polysilicon gates. Passivation layer of silicon oxynitride is deposited by
Gate poly etching is done in CF 4 /O 2 plasma (Figure PECVD. The ninth mask defines bonding pad openings,
25.2(f)). The selectivity requirement is not very demand- and plasma etching of oxynitride opens those pads. The
ing because the gate oxide is fairly thick, so the process wafer-level processing is now complete.
can be optimized for sidewall profile, rate and/or uni- The wafers will be tested electrically, at wafer level,
formity. After photoresist stripping and cleaning, a mild and non-functional chips will be inked. Dicing will
oxidation step (900 C, 10 min, dry oxidation) is per- separate the chips, and functional chips will proceed
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formed, and ca. 50 nm of oxide is grown on polysilicon. to encapsulation and packaging. Many tests cannot be
This removes plasma etch damage and re-grows gate performed at wafer level and more characterization will
oxide on source/drain areas a bit. take place on packaged chips. The cost of testing can be
The fifth photomask is actually the same mask as very high if the chips need to be tested for a multitude
the third, the PMOS threshold voltage mask: it defines of parameters.
PMOS-transistor area. This time, it protects the NMOS
areas from PMOS S/D boron-ion implantation. A high 25.1.1 CMOS variations
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dose 2 × 10 cm −2 of boron is implanted at 40 keV A prototypical 5 µm CMOS process has been described.
(Figure 25.2(g)).
There are many minor variations between different
The sixth mask is a reverse polarity version of the
CMOS manufacturers: implant doses and diffusion times
previous mask: areas that are not PMOS area are either
differ, oxide thicknesses and junction depths vary, mask
NMOS area or isolation, and can be doped by phospho-
compensations can be used, and so on. More variety
rus. The sixth mask is thus an automatically generated
enters the picture if, for example, analog CMOS is made.
mask: there is no need to design it once the PMOS mask Then some of the doping steps will be used to make
has been drawn. NMOS S/D implantation with phospho- resistors, and extra lithography masks may be needed.
15
−2
rus is at 120 keV energy with a dose of 3 × 10 cm . In more advanced analog CMOS processes, an extra
After resist stripping and wafer cleaning, a short diffu- polysilicon layer is added for resistor and capacitor fab-
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sion/oxidation step is done at 900 C for 20 min. rication. EEPROM processes also need extra polysilicon
CVD oxide (phosphorous-doped silica glass, PSG) of for the floating gate. Bipolar transistors can be added to
ca. 1 µm thickness is deposited next. PSG is a glassy a CMOS process, which will be discussed in Chapter 26.
material and above its glass transition temperature (ca.
1050 C) it will flow, resulting in beneficial smoothing 25.2 MOS TRANSISTOR SCALING
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of the top surface. This is the last high-temperature step,
and dopant profiles are now ‘frozen’. Junction depths As linewidths were scaled from 5 µm to ca. 1 µm,
of both PMOS and NMOS transistors are ca. 1 µm plasma etching replaced wet etching not only for crit-
(L/5), with source/drain area sheet resistances of ca. ical steps but for all patterning etches. Oxidation and
30 ohm/sq for NMOS and ca. 90 ohm/sq for PMOS. The diffusion times were scaled down in order to make shal-
p-well depth is ca. 4 µm and its sheet resistance is ca. lower junctions. Steps such as PSG flow were eliminated
4 kohm/sq. Threshold voltages for NMOS and PMOS because S/D diffusion spreading had to be minimized.
are ca. 1.3 V and -1.5 V, respectively. We will now discuss some issues relevant to scaling of
CMOS, both from device and fabrication point of view.
The seventh mask defines contact holes in the oxide
(Figure 25.2(h)). Wet etching in BHF is used to open
25.2.1 Lithography scaling
the contacts. Contact hole–design rules must take into
account the fact that there will be ca. 1 µm undercut in The contribution of lithography to scaling has been
this etching step. After photoresist stripping and wafer constant over the past decades. Resolution of projec-
cleaning, ca. 1 µm of aluminium is sputtered on the tion optical systems has been pushed down in a seem-
wafers. ingly continuous evolutionary process, as discussed in
The eighth mask defines metallization patterns. Alu- Chapter 9 (Equations (9.4) and (9.5)). Depth of focus
minium is etched in H 3 PO 4 -based wet etch. Aluminium (DOF) has dramatically suffered from exposure wave-
lines will be ca. 2 µm narrower than the photoresist length reduction and NA improvements, and it is major