Page 390 - Sami Franssila Introduction to Microfabrication

Moore’s Law 369

additionally, ions or electrons lead to mask charging and to grain boundary reflections, and at 100 nm linewidths,
damage. Electron scattering masks, instead of absorbing copper resistivity has been reported to increase to
masks, have been developed for EPL. This eliminates 4 µohm-cm.
many of the thickness, stress and heating problems. Still, Film thickness downscaling at the back end is driven
at an estimated 15 million-dollar price tag, EPL systems by the need to keep aspect ratios reasonable, even
will only write 15 wafers per hour. though RC-time delays inevitably increase as resistance
increases in thinner wires, and capacitance increases
when dielectrics are scaled down. Ultimate limits are
38.5 FUNDAMENTAL AND PRACTICAL LIMITS
fairly close in back-end scaling: copper is as close to
38.5.1 Linewidth and film thickness minimum resistivity as any metal can practically be,
and with dielectrics, ε = 1 (vacuum) is not so far away,
Nominal or design width is just an idealization of a
microstructure. The physical structure in silicon or in with ε = 2 materials being introduced. Superconducting
thin-film material adds its own features. These effects wiring was touted in the early 1990s as a solution to the
are more pronounced the narrower the linewidth or resistance problem, but enthusiasm waned rapidly when
the thinner the film. The smaller the details we study, the difficulties of a high-T c superconductor deposition
the more are the effects that come into play. Line and structural control became apparent.
edge roughness can become significant when compared Scaling to atomic dimensions leads to inevitable
with linewidth. In the extreme, it is partly a materials limitations. Gate oxide thickness is approaching such
limitation: chrome, photoresist and thin film on wafer are limits: because atoms are discrete, gate oxide thickness
granular to some extent, and for instance, polycrystalline is ‘quantized’ (Figure 38.4): we cannot have any gate
materials may be etched at slightly different etch rates oxide thickness, only integral multiples of atomic
for different crystal orientations, and this preferential dimensions. Putting it another way, each transistor will
have its own microscopic oxide thickness pattern, and
etching contributes to line-edge roughness.
consequently idiosyncratic microroughness that affects
In TiSi 2 formation on polysilicon, three-grain bound-
channel mobility and tunnelling currents.
aries are crucial for nucleation of the C54 phase, but if
the linewidth is narrow and the grain boundaries sparse,
nucleation is retarded. This can be battled by increasing 38.5.2 Device considerations
the annealing temperature, but this is at odds with dif-
fusion goals, and it will also change the relative rates When MOS transistors are made extremely small, the
of silicidation and surface nitridation. Polysilicon grain- ability of the gate to control the current in the channel is
size tailoring by ion implantation before titanium deposi- diminished. This can be overcome if two (or more) gates
tion can be performed or alternatively the titanium depo- are to be used instead of one, as shown in Figure 38.5.
sition process can be modified by, for example, heating, Fabrication of these devices is not obvious, and the two-
or a thin (∼nanometre) intermediate layer of molybde- gate version can exist in various configurations, with the
num can be deposited between titanium and polysilicon gates parallel to the silicon surface or vertical.
to modify nucleation kinetics. Yet another method is So far, very little attention has been paid to the
ion beam mixing: the interface between the poly and MOSFET channel, but of course, the channel can be
titanium is modified by ion implantation after metal improved and tailored just like gate oxide or junctions.
deposition. The maximum projected range should coin- Strained silicon is an actively studied channel material.
cide with the film interface for maximum modification. As discussed in connection with thin-film stresses,
When linewidth scaling is continued, the relative Si 1−x Ge x alloys have lattice constants larger than silicon
importance of physical effects changes. Current con- and they are under compressive stress, and consequently
duction in a 1 × 1 µm cross-sectional conductor line is the silicon on Si 1−x Ge x will be under tensile stress. This
fully characterized by classical ohmic description. Nar- tensile stress introduces energy split in the conduction
rower lines and thinner films reach a limit at which band of silicon, which leads to mobility enhancement,
the surface scattering contribution to resistance becomes for electrons by a factor of 2 and for holes by a factor
important, and in the 10 nm-size range, quantum effects or 4 (depending on germanium content, doping level
come into play and single electron conduction can be and field strength). Higher operating frequency could be
seen. The characteristic scale for non-classical effects is obtained from MOSFETs without lithographic scaling
the mean free path, which is 40 nm for copper and 15 nm (Figure 38.6).
for aluminium. However, some deviation from classical The smallest MOSFETs fabricated to date, have 6 nm
behaviour has been seen even at 500 nm, probably due gate lengths, and simple ring-oscillator circuits with