Page 392 - Sami Franssila Introduction to Microfabrication

Moore’s Law 371

26 nm gates have been made, too. The process used SOI limits. In a circuit with 1 000 000 000 devices, tails
wafers with 6 nm ±2 nm thick device silicon layer, and of statistical distributions can easily cause circuits to
150 nm buried oxide. Gate oxide EOT was 1.2 nm. The fail: there are 20 devices that have variations larger
gate was defined by optical lithography at λ = 248 nm, than six standard deviations. In very small volumes,
using resist trimming technique, similar to the one distribution of atoms becomes a source of variation: in
described in Figure 10.8. a 100 nm linewidth MOS transistor, the volume under
the gate is ca. 100 nm × 500 nm × 10 nm (L eff × W eff ×
inversion layer thickness), and the channel-doping level
38.5.3 Statistics and yield 18 3
is N A ≈ 10 / cm , which translates to ca. 500 dopant
atoms only. The small number of dopants in itself leads
Yield is tied to the number of process steps, which have
to detectable fluctuations in the threshold voltage, but
been increasing constantly. With 25 lithography steps,
the random positions of dopant atoms also must be
and ca. 500 steps altogether, individual step yield has to
considered. Standard deviation of the threshold voltage
be very high. This is putting more and more demands
V T is given by
on metrology: process monitoring precision and speed
have to be increased so that more wafers can be −8 0.4
σV T = 3.19 × 10 t ox N / L eff W eff [V ] (38.2)
checked. However, scaling also introduces new aspects A
that need to be measured: for example, junction depth Continued scaling to smaller dimensions together
is a too simple one-dimensional measure; it needs to with the increase in the number of devices per
be complemented by the junction abruptness yardstick. chip rapidly leads to situations in which not all
With ultra low-k films, film thickness and density are devices switch.
not enough, the pore size and pore size distribution must
be known.
38.6 IC INDUSTRY
Despite aggressive linewidth scaling, the chip area
keeps increasing. The number of defects per chip The IC industry has been growing at 17% annually
has to remain constant or decrease, which means that for over 30 years, whereas the electronics industry as
defect density has to be scaled down more aggressively a whole grows only 7% annually. For the IC industry
than linewidth. The chip area increases because of the to keep growing at its historical rate, the IC content
economic incentive to integrate as many functions as of electronics has to rise at the expense of discrete
possible on the chip, in order to reduce packaging devices, circuit boards, connectors, displays, switches
and assembly costs (as discussed in Chapter 37). At and keyboards, or else IC growth will slow down. ICs
the moment, it seems that lithographic lenses are now account for 15% of the value of electronics. Is it
limiting chip size increase: it has not been possible to reasonable to expect it to rise to 30 or to 50%, like it is
simultaneously improve resolution and to increase lens in portable electronics?
field size at the same pace. This, of course, applies
mostly to evolutionary scaling of refractive optical
systems; reflective optics, X-ray lithography or EPL Mainframe computers (1980s) 8–10% of the value
have their own scaling trends. consists of ICs
Chemicals, DI-water, process gases and targets have Personal computers (1990s) 25–33% of the value
been ‘scaled’ to higher and higher purity levels. Metal consists of ICs
impurity levels have been reduced by a factor of 100 in Handheld devices (2000s) 40–50% of the value
four technology generations. Measurement of minutiae consists of ICs
impurities must be available for gases, liquids and
solids. Cleanrooms have been ‘scaled’ to higher and Measures from IC manufacturing can be used to
higher standards of purity. Cleanliness today is so high check if the rate of introduction of novel devices is
that particle measurements have hit the barrier: there slowing down. The ramp rate of production to high
are simply not enough particles to statistically assess volumes is one measure. There are some hints that this
particle purity. With increasing cleanroom cost, there has might be slowing down. The cost of a fab compared to
been an incentive to find alternative operation modes. the revenue it is assumed to generate during its lifetime
Integrated processing is one such approach, keeping the is another measure. Obviously, the former must be kept
wafers under controlled ambient at all times. to a fraction of the latter but recently the cost of the
Statistics with extremely large or extremely small fab has been rising faster than the revenue. Both these
quantities can have some surprises even before ultimate measures are tricky because the IC industry is very