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52 MEMS and Microstructures in Aerospace Applications

long or wide structures, etch-release holes are frequently incorporated into the
structural layers to provide access for HF to the underlying sacrificial silicon
dioxide. This will reduce the etch-release process time. Since the MEMS device
is immersed in a liquid during the release etch, an issue is the adhesion and stiction
25
of the MEMS layers upon removal from the liquid release etchant. Since poly-
silicon surfaces are hydrophilic the removal of liquids from the MEMS device can
be problematic. Surface tension of the liquid between the MEMS layers will
produce large forces, pulling the layers together. Stiction of the MEMS layers
after the release etch can be addressed in several ways:

. Making the MEMS device very stiff to resist the surface tension forces
. Fabricating a bump (i.e., dimple) on the MEMS surfaces, which will prevent
the layers from coming into large area contact
. Using a fusible link to hold the MEMS device in place during the release etch,
which can be mechanically or electrically removed subsequently 26
. Using a release process, which avoids the liquid meniscus during drying, such
as supercritical carbon dioxide drying 27 or freeze sublimation 28
. Use a release process that will make the surface hydrophobic, by using self-
assembled monolayer (SAM) coatings. 29 It has been reported that SAM
coatings also have the affect of reducing friction and wear

3.5.1 SUMMiT Ve
An example of a surface micromachined MEMS fabrication process is SUMMiT
(Sandia Ultra-planar, Multi-level MEMS Technology), a state-of-the-art five-level
surface micromachine process developed by Sandia National Laboratories. 30,31
SUMMiT processing utilizes standard IC processes, which are optimized for the
thicker films required in MEMS applications. Low-pressure chemical vapor
deposition (LPCVD) is used to deposit the polysilicon and silicon dioxide films.
Optical photolithography is utilized to transfer the designed patterns on the mask
to the photosensitive material that is applied to the wafer (e.g., photoresist or
resist). Reactive ion etches are used to etch the defined patterns into the thin
films of the various layers. A wet chemical etch is also used to define a hub
feature, as well as the final release etch of the SUMMiT process. Figure 3.14
schematically shows the layers and features in the SUMMiT V process. The
SUMMiT V process uses 14 photolithography steps and masks to define the required
features. Table 3.5 lists the layer and mask names and a summary of their use.
The SUMMiT fabrication process begins with a bare n-type, <10 0> silicon
wafer. A 0.63 mm layer of SiO 2 is thermally grown on the bare wafer. This layer
of oxide acts as an electrical insulator between the single-crystal silicon substrate
and the first polycrystalline silicon layer (MMPOLY0). A 0.8 mm thick layer of
low-stress silicon nitride (SiN x ) is deposited on top of the oxide layer. The nitride
layer is an electrical insulator, but it also acts as an etch stop protecting the
underlying oxide from wet etchants during processing. The nitride layer can
be patterned with the NITRIDE_CUT mask to establish electrical contact with the

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