Page 31 - Organic Electronics in Sensors and Biotechnology

8 Chapter One

for these devices with such small dimensions at different tempera-
tures down to 4.2 K. On the other hand, there have been many reports
on the transport of various organic semiconductor materials with
large channel length transistors at low temperatures with different
measurement techniques. 41–45 To investigate the possible transport
mechanisms which become dominant when scaling the device size
from micron-scale down to nanoscale, we systematically fabricated
thin-film field-effect transistors of a series of channel lengths from 5 μm
down to 80 nm, with pentacene as the active organic semiconductor
layer. All the investigated transistors of different channel lengths
were fabricated by the same nominal geometry ratio W/L = 10, for
the purpose of consistent scaling.
Bottom-contact structures are preferred in the fabrication of
nanoscale organic/polymeric thin-film field-effect transistors. To fab-
ricate submicron devices, e-beam lithography is a commonly used
tool in defining the electrode pattern. For top-contact structures,
however, the lithography step has to be performed on top of the pre-
deposited active organic layer, which can degrade the organic material
upon immersion in solvent solutions during developing and liftoff
steps, or damage the organic material while evaporating metal
atoms onto it. Hence, the bottom-contact configuration is chosen over
the top-contact one. A heavily doped n-type silicon wafer serves as
the mechanical substrate and the gate. The single-crystal silicon sub-
strate was heavily doped by n-type dopants (phosphorous or arsenic)
so that the depletion in the silicon as a gate was minimized. To serve
as conductive gate, the doping concentration of the Si substrate
3
18
needs to be higher than 3.74 × 10 /cm for phosphorous dopant or
3
18
8.5 × 10 /cm for arsenic dopant. A SiO layer that serves as the gate
46
2
dielectric was then thermally grown on the substrate. Transistors of
channel length greater than 1 μm utilize a 100 nm thermally grown
SiO layer as the gate dielectric, whereas for nanoscale transistors, a
2
5 nm SiO layer as the gate dielectric was grown by rapid thermal
2
annealing in dry oxygen. The electrode patterns were made by e-beam
lithography. Metal electrodes with an adhesive layer (Ti was chosen)
that improves sticking to SiO were then deposited by e-beam evapo-
2
ration in high vacuum, followed by a liftoff process. If the Ti layer is
thinner than the accumulation channel depth, then carriers are
injected directly from the high work function metal layer atop the Ti
layer, which remarkably reduces the series resistance. Therefore the
Ti layer was chosen to be 1 to 3 nm thick. Gold was chosen as the
electrode material, due to its high work function aiding the injec-
tion of holes into organic material, its air stability, and its ability to
form an ohmic contact with organic materials under certain optimal
conditions.
Device fabrication was completed by subliming small organic
molecules (e.g., pentacene) at different growth rates and different
substrate temperatures for different grain sizes. Slower growth rates