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PLASMA ETCHING

PLASMA ETCHING 12.17

coupled plasma and electron cyclotron resonance (ECR) TABLE 12.5 Etch Rates and Selectivity
reactor configurations, 82,83 to take advantage of the capability in the Pulsed 40 MHz Plasma
of independent control of the ion density and energy. The con-
figurations allow for lower ion energies (dc bias <50 V) at Etch rates
higher ion densities. While the lower ion energies facilitate low GaAs etch rate 618.6 Å/min
damage etching, the GaAs etch rates in high-density plasma AlGaAs etch rate 1.6 Å/min
are high, i.e., >1000 Å/min, making it difficult to control the Si N etch rate 14.2 Å/min
3 4
etch process for thin film (<1000 Å) applications. Resist Etch rate 30.9 Å/min
An improved approach is to use a parallel plate configura-
tion powered at 40.68 MHz in a time-modulated fashion. 84 Selectivity
The high-frequency RF excitation results in lower dc bias GaAs : AlGaAs 399:1
voltages, <30 V, compared to the 13.56-MHz RIE. In order to GaAs : Si N 4 44:1
3
reduce the GaAs etch rate to controllable levels for thin film GaAs : resist 20:1
applications, the high-frequency RF power is pulsed. The etch
rate during the “on” period remains unchanged (~1000
Å/min), while the etch rate during the off period is essentially zero. The average etch rate is thus a func-
tion of the pulse duty cycle and can be lowered. Table 12.5 summarizes the etch performance achieved
using this approach.

Backside Etch of GaAs and Related Materials. GaAs is a relatively poor thermal conductor, making
it difficult to remove heat efficiently from power devices. A solution is to form vias from the wafer back-
85
side to the frontside circuitry and metallize the vias. For a via etch process, since it is necessary to etch
approximately 100 µm deep into the GaAs substrates, a high etch rate is essential to ensure a reasonable
wafer throughput. Also, selectivity to a photoresist mask of at least 10:1 is desirable for photoresist pro-
cessing. For good metallization, the via wall should have a sloped profile, with some control over the
slope to accommodate the conflicting requirements of the wall slope and reduced via dimensions.
As illustrated in Fig. 12.14, a combination of high GaAs etch rate, controlled selectivity to the
85
resist mask, and a sloped resist profile facilitates sloped via etching. The high etch rate is achieved
using an ICP source. Control over selectivity is through independent control of the bias voltage. The
resist profile can be manipulated through hard bake. One of the issues in via etching is that pillar for-
mation is sometimes observed. 86 Pillar formation can arise from a number of causes including
residues from upstream operations, material effects, and the plasma etching process. It is potentially
harmful to the reliable metallization of the vias. It has been demonstrated that pillar formation can
be reduced through the use of higher Cl flows, lower process pressures, and higher ICP powers. 87
2
Lower RF bias powers during the etch initiation step also significantly reduce pillar formation.
12.4.2 Etching of InP Materials

Indium-containing multilayer structures (including InP, InGaAs, and InGaAsP) are now prevalently
used for long wavelength optical devices. Due to the difficulties associated with dry etching In-based
materials, manufacturing has traditionally been low volume at high cost. In recent years, the demand
for high etch rate for improved throughput is on the rise. For example, plasma etching of InP mate-
rials now involve processes in ICP sources using hydrocarbon-(CH /H -) and halogen (Cl-, Br-, and
2
4
I-)-based chemistries. 79,88
• CH /H chemistry results in a smooth surface due to near equal removal rates of volatile In(CH )
4 2 3 3
and PH products. The etching rate is considered slow at approximately 500 Å/min and polymer
3
deposition causes contamination of both the etching module and the samples. 89,90
• Cl chemistry is an alternative to etching In-based materials. Elevated temperatures are typically
2
required to obtain high etching rates and acceptably smooth surfaces. The use of Cl -based
2
chemistries at substrate temperatures of 225°C to etch InP/InGaAsP with smooth surfaces and high
etching rates has been reported. 91,92
93
• HBr chemistries are also used to etch InP. The etch rate is approximately 1000 Å/min, along with
a smooth surface and a positively sloped profile, at room temperature. As the substrate temperature
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