Page 191 - A Comprehensive Guide to Solar Energy Systems
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Chapter 9 • Crystalline Silicon Solar Cell and Module Technology   193



                 process. After diffusion, a phosphosilicate glass remains at the surface, but that is usually
                 etched off with diluted hF.
                   The next step is the surface passivation with a dielectric layer. A negatively charged
                 dielectric (e.g., Al 2 O 3 ) on P-type surface or a positively charged dielectric (SiO 2  or Si 3 n 4 ) on
                 n-type surface is desirable because they create an accumulation layer below the silicon
                 surface and decrease the surface recombination effect. It can be combined with depo-
                 sition of antireflection coating on the surface after low-level phosphorous diffusion. An
                 effective surface passivation in combination with antireflection layer fabrication can be
                 made by depositing a silicon nitride layer using a PeCVD (plasma-enhanced chemical va-
                 por deposition) technique from a mixture of silane and ammonia:
                                             3SiH 4 + 4NH 3 → SiN 4 +  12 H 2                                                                3Sih 4 +4nh 3 →Si 3 n 4 +12   h 2
                                                            3
                   This step is very important for muticrystalline wafers cells. Atomic hydrogen from the plas-
                 ma interacts with impurities and defects and passivates the grain boundaries. At this fabrica-
                 tion step, an amorphous silicon nitride film is produced with up to 40 atomic percent of hy-
                 drogen (the so-called Sin x  layers). The layer composition influences the refraction index and
                 it can be controlled during the layer fabrication. The layer thickness is approximately 75 nm.
                   Front metallization is a key process in c-Si cell fabrication. The contact grid on the front sur-
                 face should produce very narrow but thick and highly conductive metal lines with a low con-
                 tact resistance to Si. This is mostly done by screen printing the phosphorous-doped silver paste
                 on a n-type layer covered with a silicon nitride layer. The paste consists of 60%–80% conduct-
                 ing material (a powder of silver particles of approximately 1 µm), 5%–10% glass frit (a powder
                 of different oxides of lead, bismuth, silicon, etc.) organic solvent, and an organic binder that
                 binds the active powder before thermal activation. The present trend is to decrease the silver
                 consumption by reducing the finger width and decreasing the silver content in the busbars.
                   On the back surface, a layer of the paste containing aluminum is deposited by screen
                 printing. This paste either contains silver allowing soldering metallic contacts during a
                 module assembly, or strips of silver paste are printed in the second step over the Al con-
                 taining paste. After each print, wafers are dried at a temperature of approximately 200°C.
                   The screen-printed paste layers are fired through the nitride layer to make a good elec-
                 trical contact with the underlying semiconductor at a temperature over 800°C. At the back
                                                                                           +
                 surface, the Al-Si eutectic is formed and during cooling recrystallized Al-doped P  layer
                 creates the back surface field and ensures a good contact. At the front surface, particles of
                                                                                  +
                 silver (embedded in a compact amorphous glass) come in contact with n  silicon layer en-
                 suring a low contact resistance to Si. The composition of the pastes and the thermal profile
                 of cofiring must be adjusted very carefully.
                   After contact fabrication, the possible shunts on the edge of the wafer must be removed.
                 It is done mostly by laser ablation of the wafer edges. An alternative is plasma etching of
                 wafer edges after the phosphorous diffusion.
                   The final step is measuring I–V characteristics of the cell using a solar simulator and
                 sorting cells into groups according their output (e.g., by cell current at fixed voltage near
                 the maximum power point). It is important that the modules are built from cells with a
                 minimum mismatch of characteristics. The process sequence is demonstrated in Fig. 9.12.
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