Page 69 - An Introduction to Microelectromechanical Systems Engineering
P. 69

48                                                       Processes for Micromachining

                    LPCVD silicon nitride is an excellent masking material against etching in KOH.
                 Silicon dioxide etches at about 10 nm/min and can be used as a masking layer for
                 very short etches. Photoresist is rapidly etched in hot alkaline solutions and is there-
                 fore not suitable for masking these etchants.
                    Alkali hydroxides are extremely corrosive; aluminum bond pads inadvertently
                 exposed to KOH are quickly damaged. It should be noted that CMOS fabrication
                 facilities are very reluctant to use such etchants or even accept wafers that had previ-
                 ously been exposed to alkali hydroxides for fear of contamination of potassium or
                 sodium, two ions detrimental to the operation of MOS transistors.
                    In the category of ammonium hydroxides, tetramethyl ammonium hydroxide
                 (TMAH, N(CH ) OH) exhibits similar properties to KOH [7]. It etches {111} crys-
                               3 4
                 tallographic planes 30 to 50 times slower than {100} planes. The etch rate drops by a
                                                               −3
                                                           20
                 factor of 40 in heavily p-doped silicon (~1 ×10 cm ). A disadvantage of TMAH is
                 the occasional formation of undesirable pyramidal hillocks at the bottom of the
                 etched cavity. Both silicon dioxide and silicon nitride remain virtually unetched in
                 TMAH and hence can be used as masking layers. It is advisable to remove native sili-
                 con dioxide in hydrofluoric acid prior to etching in TMAH because a layer just a few
                 nanometers thick is sufficient to protect the silicon surface from etching. TMAH
                 normally attacks aluminum, but a special formulation containing silicon powder or
                 a pH-controlling additive dissolved in the solution significantly reduces the etch rate
                 of aluminum [8]. This property is useful for the etching of silicon after the complete
                 fabrication of CMOS circuits without resorting to the masking of the aluminum
                 bond pads.
                    EDP is another wet etchant with selectivity to {111} planes and to heavily
                 p-doped silicon. It is hazardous and its vapors are carcinogenic, necessitating the use
                 of completely enclosed reflux condensers. Silicon oxides and nitrides are suitable
                 masking materials for EDP etching. Many metals, including gold, chromium, cop-
                 per, and tantalum, are also not attacked in EDP; however, the etch rate for alumi-
                 num is at about 0.3 µm/min for the formulation given in Table 3.2.
                    Etching using anisotropic aqueous solutions results in three-dimensional faceted
                 structures formed by intersecting {111} planes with other crystallographic planes.
                 The design of the masking pattern demands a visualization in three dimensions of
                 the etch procession. To that end, etch computer simulation software, such as the
                 program ACES™ available from the University of Illinois at Urbana-Champaign,
                 are useful design tools.
                    The easiest structures to visualize are V-shaped cavities etched in (100)-oriented
                 wafers. The etch front begins at the opening in the mask and proceeds in the <100>
                 direction, which is the vertical direction in (100)-oriented substrates, creating a cav-
                 ity with a flat bottom and slanted sides. The sides are {111} planes making a 54.7º
                 angle with respect to the horizontal (100) surface. If left in the etchant long enough,
                 the etch ultimately self-limits on four equivalent but intersecting {111} planes, form-
                 ing an inverted pyramid or V-shaped trench. Of course, this occurs only if the wafer
                 is thicker than the projected etch depth. Timed etching from one side of the wafer is
                 frequently used to form cavities or thin membranes. Hourglass and oblique-shaped
                 ports are also possible in {100} wafers by etching aligned patterns from both sides of
                 the wafer and allowing the two vertical etch fronts to coalesce and begin etching
                 sideways, then stopping the etch after a predetermined time.
   64   65   66   67   68   69   70   71   72   73   74