Page 459 - DSP Integrated Circuits

444 Chapter 10 Digital Systems

10.4.3 Metastability

A bistable device may enter into what is referred to as the metastable state where
the output is undefined—i.e., it is not properly denned in terms of the inputs [3,9].
Two types of metastability can occur: analog and oscillatory [23]. The former
causes the output of the device to stay at an electrical level near the input thresh-
old voltage, while the latter causes the output to toggle repeatedly between the
two logic levels. In both cases, the bistable device settles to either valid state,
within a resolving time that is a function of the input timing and certain circuit
parameters.
This anomalous behavior, called metastability, is unavoidable in any type of
bistable device, and the resolving time needed for the device to settle to either
state is, in principle, unbounded. However, several design measures can be taken
to keep undesired effects within certain limits [11]. The main issue is to use cir-
cuits that have a high gain-bandwidth product. Degradation of the power supply
voltage and increased chip temperature are highly detrimental.

10.5 CLOCKING OF SYNCHRONOUS SYSTEMS

Digital (logic) systems are in principle built using combinational and sequential
networks. The inputs and outputs of the networks are interconnected via storage
elements. These storage elements carry information from one evaluation phase to
the next phase, in a similar way to delay elements in digital filter algorithms. Sys-
tems in which the information flow is fully controlled by the clock signals are
called synchronous systems. The storage elements can be implemented as latches
or flip-flops, as just discussed. Several different clocking schemes have been devel-
oped to control the information flow [18, 25]. The most common clocking schemes
will be discussed next.

10.5.1 Single-Phase Clock

By using storage elements (SEs) controlled by one or more clock signals, a variety of
clocking schemes can be obtained. A straightforward clocking scheme is the single-
phase clocking illustrated in Figure 10.14. For simplicity, the lines in the figures
may represent one or several signals. Obviously, this prevents the circuit from work-
ing properly if the storage elements are implemented with latches that become
transparent during a part of the clock cycle. If the transparent phase is shorter than
the internal delay in the combinational logic, the circuit may work, but this is a very
risky situation and should be avoided. Notice that the basic idea with digital circuits
is that they should be robust and insensitive to circuit and timing variations.
Signal delays incurred in the logic circuitry may create race problems. Another
source of problems results from delay difference incurred by clock signals that have
propagated through different paths. This type of delay is called clock skew. Both of
these problems will ultimately limit the maximum clock frequency. Race problems
can be reduced by using circuits with short critical paths between the clocked ele-
ments. This can be accomplished by introducing pipelining at the circuit level. The
clock skew problem can be reduced by using proper clocking strategies. The choice of
logic style is also important to minimize the effect of clock skew.