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270 CHAPTER 6 / NONARITHMETIC COMBINATIONAL LOGIC DEVICES

number of bits. As an example, the output expressions for a cascadable 4-bit comparator
become

i=0 i = l i=2
_ _
= B} = eq- f~[(A, Q B/) = (A^B) • (A < B) (6.23)
i=0
3 3 3
(A < B) = It • JT(A,- O B{) + Aofio ]|(A» O #/) + A\B\ T|(A,- O B{]
i=0 i=l i=2

where

3 ^
[~[(A ( O B,-) = (A 0 O Bo)(Ai O B,)(A 2 O fl 2)(A 3 O
i=0

and
3
Ai O £,) = (A 2 O fl 2)(A 3 O 5 3), etc.
(=2

Implementation of Eqs. (6.23) is given in Fig. 6.29, using three-level NAND/NOR/EQV
logic and limiting fan-in to 5. Here, the gate/input tally is 23/67, excluding inverters.
The commercial chip that is equivalent to the cascadable 4-bit comparator of Fig. 6.29 is
the 74xx85. Though the two differ somewhat in the logic circuit makeup, they function in
exactly the same way. Either can be cascaded to form a comparator of any number of bits in
multiples of four bits. Shown in Fig. 6.30 is an 8-bit comparator formed by cascading two
4-bit comparators in series. Notice that the inputs to the least significant stage are required
to be at the fixed logic levels shown.
Combining three or more comparators in series suffers significantly in propagation delay.
Much better is the series/parallel arrangement shown in Fig. 6.31. Here, six 4-bit compara-
tors are combined to form a 24-bit comparator where no more than two comparators are
placed in series and all inputs and outputs are active high. In this case, a dominant A or
B word is picked up by one of the five stages in ascending order of significance and is is-
sued as either (A > B), (A = B), or (A < B) from the MSB stage of the output comparator.
Words A and B of equal magnitude are picked up by the least significant stage and issued by
the output comparator as (A = B). The series/parallel comparator arrangement in Fig. 6.31
is justifiable on the basis of path delay arguments when the alternative is considered —
namely, the series configuration of six 4-bit comparators. Notice that not all of the 24 bits
of the comparator need be used. Any size A, B words up to 24 bits can be compared by
using the comparator of Fig. 6.31. The only requirement is that words A and B be of equal
length and that MSB inputs not in use be held at 0(H).