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A 3 AS A, A 0 B 3 B 2 B, B 0
(H) (H) (H) (H) (H) (H) (H) (H)
gt(H)
(A>B)(H)
eq(H) - -P> - (A=B)(H)
(A<B)(H)
FIGURE 6.29
Three-level logic circuit for the cascadable 4-bit comparator by using NAND/NOR/EQV logic with
a fan-in limit of 5.
271
