Page 493 - Engineering Digital Design

10.10 ASYNCHRONOUS PRESET AND CLEAR OVERRIDES 463

Here, a handshake configuration exists between the master and slave stages. A handshake
configuration occurs when the output of one FSM is the input to another and vice versa. This
FSM is susceptible to a serious error catching problem: In the reset state, if CK is active
and a glitch or pulse occurs on the J input to the master stage, the master stage is irreversibly
set, passing that set condition on to the slave stage input. Then when CK goes inactive, the
output is updated to the set state. This is called 1 's catching and is an unrecoverable error,
since the final set state was not regulated by CK. Similarly, in the set state, if CK is active
and a glitch or pulse occurs on the K input, the master stage is irreversibly reset, passing
that reset condition on to the slave stage input. Then when CK goes inactive, the output is
updated to the reset state. This is called O's catching and is also an unrecoverable error.
Because of the error catching problem just described, the MS JK flip-flop in Fig. 10.50b,
derived from the "handshake" state diagrams in Fig. 10.50a, should never be considered
for application as a memory element in a synchronous state machine. If an MS JK flip-flop
is needed as the memory element, it is best designed by using Eq. (10.11) and Fig. 10.42a
for conversion from an MS D flip-flop that has no error catching problem. Also, because
the MS D flip-flop can be implemented by using transmission gates and inverters, as in
Fig. 10.35, the conversion to a MS JK can be accomplished with a minimum amount of
hardware.

1 0.1 0 ASYNCHRONOUS PRESET AND CLEAR OVERRIDES

There are times when the flip-flops in a synchronous FSM must be initialized to a logic 0 or
logic 1 state. This is done by using the asynchronous preset and clear override inputs to the
flip-flops. To illustrate, a D latch is shown in Figs. 10.5 la and 10.5 Ib with both preset and
clear overrides. If the flip-flop is to be initialized a logic 0, then a CL(L) = 1(L) is presented
to NAND gates 1 and 4, which produces a mixed-rail reset condition, Q(H} = 0(//) and
Q(L) = 0(L) while holding PR(L) = 0(L). Or to initialize a logic 1, a PR(L) = 1(L) is
presented to NAND gates 2 and 3, which produces a mixed-rail set condition, Q(H) = l(H)
and <2(L) = 1 (L), but with CL(L) held at 0(L). Remember from Subsection 10.4.4 that 5(L)
and /?(L) cannot both be 1(L) at the same time or else there will be loss of mixed-rail output.
Thus, the CL,PR =1,1 input condition is forbidden for this reason. The following relations
summarize the various possible preset and clear override input conditions applicable to any
flip-flop:
CL(L) = 1(L) CL(L) = 0(L)
Initialize 0 Initialize 1
PR(L) = 0(L) PR(L) = 1(L)
(10.14)
CL(L) = 0(L) CL(L)=1(L)
Normal Operation Forbidden
PR(L)=l(L)
The timing diagram in Fig. 10.5 Ic best illustrates the effect of the asynchronous preset
and clear overrides. In each case of a PR(L) or CL(L) pulse, normal operation of the latch
is interrupted until that pulse disappears and a clock triggering (rising) edge occurs. This
asynchronous override behavior is valid for any flip-flop regardless of its type or triggering
mechanism, as indicated in Fig. 10.52. For all flip-flops, these asynchronous overrides act
directly on the output stage, which is a basic cell.