Page 551 - Engineering Digital Design

11.6 CLOCK SOURCES AND CLOCK SIGNAL SPECIFICATIONS 521

0.1% precision will be crystal controlled. Quartz crystals, which can be cut (dimensioned)
to oscillate at a specific frequency to a great precision, are an ideal choice for use in a
crystal-controlled oscillator. Such specific frequencies can be in the megahertz range.
The duty cycle of a clock waveform is defined by the relation
T
Duty cycle = — ^- x 100 (in percent), (H-4)
TCK
where T Active is the active portion of a clock cycle and T CK is the clock period, both given
in seconds. Thus, a 50% duty cycle means that the active and inactive portions of the clock
waveforms are equal. Duty cycle control by an oscillator circuit is important but requires
additional circuit elements and raises the cost of the device.
An oscillator, such as that in Fig. 1 1 .26b, provides the reference frequency /o that may
have to become some multiple of /o to achieve the high frequencies required by modern
sequential machines. Dividing frequency is easily accomplished by using a counter, as
explained later in Section 12.3. However, obtaining an integer multiple of the reference
frequency, n/o, is a much more complex operation. One means of accomplishing this is to
use a phase-locked loop with a programmable divider in the feedback called a frequency
synthesizer, the details of which are beyond the scope of this text. Properly designed, the
frequency synthesizer will provide all of the desirable oscillator characteristics previously
mentioned. Information on this and related subjects can be obtained in references cited in
Further Reading at the end of this chapter.

1 1 .6.2 Clock Signal Specifications

At some point in the design of a synchronous FSM, the designer must fashion the digital
electronics of the FSM to a given clock frequency or, perhaps less likely, the reverse.
In either case, it is necessary to know on what parameters an optimum clock frequency
depends. A view of Figs. 10.58 and 10.64, which are typical logic circuits for synchronous
FSMs, indicates that the clock period cannot be less than the propagation delay through
the flip-flop (including the setup time) plus the delay through the next state-forming logic.
In mathematical terms, the minimum clock period is usually evaluated from the maximum
system cycle time

r
TCK > ff mm + T/wmax + t SUmm (1 1.5)
or

= l//CK, (H.6)

where T#- max is the maximum flip-flop propagation delay, T nSmm is the maximum propagation
delay through the NS forming logic, t SUnYM is the maximum setup time (defined in Section
10.11), and Af/j is a factor of safety. The factor of safety allows for some variance in the
values used for the other parameters and for the possibility of clock skew on clock lines
to the flip-flops. The maximum flip-flop propagation delay is determined from the t phi and
tpih parameters, as illustrated for an RET D flip-flop in Fig. 1 1.27. Thus, the average value
for iff is obtained by introducing the data from Fig. 1 1.27 into Eq. (6.1), but it is clear that
Tj max = Tphi in this case. Normally, the manufactures of the flip-flop devices will provide