Page 554 - Engineering Digital Design

524 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS

To understand how the sanity circuit works, it is necessary to first focus attention on
the R-C component of the circuit in Fig. 11.28. Students in electrical engineering will
recognize this as a first-order R-C circuit, where RC is called the time constant of the
circuit. With Reset at LV and neglecting the influence of the Schmitt trigger in Fig. 11.28,
the following approximations for Vx (voltage at node X) result:
On Power Up at time t = 0 (power Up/Dn switch connected to the supply voltage + V 5
with Reset set to LV):

Vx(t)=V s{l-e' t/RC } (11.7)

@t = 0+ V x = 0V, therefore X = 0(H) = 1(L) = Sanity(L)
@t = 5RC V x = V s, therefore X = !(//) = 0(L) = Sanity(L)

On Power Down or Reset at time t = 0 (power Up/Dn switch connected to ground or
Reset is set to HV, one or the other):
@t = 0+ V x = V s, therefore X = l(H) = 0(L) = Sanity(L)

@t>0 V x = 0V, therefore X = 0(//) = 1(L) = Sanity(L)

On power up with the Reset input to the NMOS at LV, the capacitor is charged through the
resistance R since the diode is nonconducting in reverse bias. (Recall that a diode conducts
in forward bias only, the direction of the "arrow" in its symbol.) The result is Eq. (11.7)
for the approximate time dependent rise of voltage at node X. In effect, it is these voltage
values at node X that are presented to the preset and clear overrides of the flip-flops during
initialization or reset of the memory flip-flops, as in Figure 11.28. In the logic domain this
means that X(L) = Sanity(L). Notice that power down or reset is abrupt with no significant
exponential decay in voltage at node X. This is so because the capacitor is discharged to
ground either through the diode on power down or through the NMOS switch at reset. In
either case the discharge of the capacitor is extremely rapid. An abrupt power down or reset
is important during short power interruptions so as to ensure that proper initialization of the
flip-flops occurs during the power recovery event.
Thus, for a short period of time, say <3RC, each flip-flop is initialized to either a logic
0 or a logic 1 via the Sanity(L) input to its active low asynchronous clear or preset override.
Then, beyond a period of about 5RC all flip-flops are free to function normally since their
active low preset and clear overrides are now at 0(L). Typical values for RC may range from
the millisecond to the microsecond range by adjusting the values for R (in ohms) and C (in
farads). Values of the time constant that are too short may fail to properly initialize the flip-
flops in the memory, and values too large may cause unnecessary delays in the initialization
process. Therefore, it is worthwhile for the designer to match the RC time constant to the
logic family of the flip-flop memory. Note that Sanity(H) signals (see Fig. 11.28) are useful
in initializing asynchronous FSMs as described later in Section 14.11.
The results of the foregoing discussion are illustrated in Fig. 11.29. Here, V pu is the
power-up switching threshold of the Schmitt trigger, and V pd is the power-down switching
threshold. Unlike an inverter whose upward and downward bound switching thresholds are