Page 561 - Engineering Digital Design

11.9 APPLICATIONS TO THE DESIGN OF MORE COMPLEX STATE MACHINES 531

review the contents Section 10.6, in particular the mapping algorithm, before continuing in
this section.

Part I. Understand the Problem

1. Develop a thorough understanding of the functional requirements and I/O specifica-
tions of the FSM to be designed. The construction of block diagrams can be helpful
in this regard.
2. Note any specific timing constraints that must be met. Not all information regarding
timing constraints and timing problems may be apparent initially and may have to be
gathered as the design proceeds.

Part //. Construct a State Diagram

1. Choose a model (e.g., a Moore or Mealy model) and construct a fully documented
state diagram that meets the requirements of the algorithm and timing constraints
of the FSM. Use flowcharts and timing diagrams if necessary. Several attempts at
constructing a state diagram may be necessary in obtaining the one best suited to the
design.
The use of algorithmic state machine (ASM) charts and state tables can be very
useful in arriving at a suitable state diagram. Section 11.10 discusses ASM chart
nomenclature and the use of state tables together with their relationship to the state
diagram and to a hardware description language such as VHDL.
2. If asynchronous inputs are present, make certain that the branching dependency and
conditional output rules, given in Subsection 11.4.1, are obeyed. Decide at this point
if any or all of the asynchronous inputs are to be synchronized — usually, they will
have to be synchronized.

Part III. Obtain the Output Functions

1. Choose the NS and output logic hardware and memory devices to be used and then
obtain the output functions. Knowing how the output functions are to be implemented
and the character of the flip-flops to be used can influence the design strategy with
regard to static hazards in the output, as discussed in Section 11.3.
2. If logic noise is determined to be a problem in the output signals of the FSM, corrective
action must be taken.
(a) If output race glitches (ORGs) are present, eliminate them by using one or more
of the methods considered in Subsection 11.2.2.
(b) If static hazards exist in the output functions, eliminate them by adding hazard
cover to the output functions as discussed in Section 11.3, or use the filtering
method illustrated in Fig. 11.7. If one or more of the s-hazards are of the internally
initiated type, a proper choice of flip-flops can be used to eliminate them, as
indicated in Subsection 11.3.2.

Part IV. Obtain the Next-State Functions Plot the NS K-maps by using the mapping
algorithm given in Section 10.6 and then extract minimum or reduced cover for the NS