Page 562 - Engineering Digital Design

532 CHAPTER 11 /SYNCHRONOUS FSM DESIGN CONSIDERATIONS

functions. Implement these results by using discrete logic as in Section 10.12, or by using
a PLD as discussed later in Section 13.2. If a ROM is to be used to implement the NS and
output logic, program the ROM directly from the state diagram (also discussed in Section
13.2). If a shift register or counter is used as the memory, obtain the NS logic according to the
procedure discussed later in Sections 13.3 and 13.4. For one-hot designs, the NS and output
logic functions are read directly from the state diagram or ASM chart (see Section 13.5).

Part V. Select the Circuits Necessary for I/O Conditioning and Initialization/Reset
1. Select the appropriate input debouncing and synchronizing/stretching circuits and the
output filtering hardware to be used, if any. Refer to Sections 11.2, 11.4, and 11.8 for
assistance in making the proper choice. Make certain that all timing requirements are
met.
2. Select the initialization/reset hardware (sanity circuit) appropriate for the design as
discussed in Section 11.7.

Part VI. Construct the Logic Circuit Construct a complete logic circuit of the FSM,
preferably in mixed-logic notation, and make any necessary comments for future reference.
Avoid the use of unusual logic symbols unless accompanied by appropriate labels.

Part VII. Test the Logic Circuit Simulate the logic circuit to ascertain whether or not it
operates correctly in the logic domain. Use both gate-level and SPICE-level simulations, in
that order, if possible. The final test, of course, is that in real time by using testing equipment
such as a waveform analyzer.

11.9.2 Design Example: The One- to Three-Pulse Generator
The problem is to design a pulse generator that will issue one, two, or three clean, discrete
pulses or no pulses depending on the settings of two switches, SWi and SWo. A general
description of the pulse generator is provided by the block diagram in Fig. 11.35a and by
the operation table in Fig. 11.35b. It is required that each pulse issued by this FSM be of
the same active duration as clock, and that the two switches SW] and SWo be preset well
in advance of the start switch S command. Thus, SWi and SWo need not be debounced or
synchronized. It is also required that these two preset switches remain fixed at their proper
logic level for a period of time exceeding that required for a pulse generating sequence. It is
further required that the pulse generator be initialized into a non-output state, and that the
start signal S be returned to the inactive condition following a pulse-generating sequence
and before initiating another pulse sequence.
The switch inputs S, SWi, and SW 0 are asynchronous inputs. However, only the start
switch S is required to be debounced and synchronized. It is best to synchronize S anti-
phase to the FSM memory, which is arbitrarily chosen to be FET flip-flops, as indicated
in Fig. 11.35a. The timing diagram in Fig. 11.35c illustrates the operation of the pulse
generator by showing one- and three-pulse generations in agreement with the operation
table in Fig. 11.35b. Notice that the first pulse of a sequence is issued with the next active
portion of the clock following an active Start command and the sampling of the preset
switch logic levels.