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Stacked ICs and Packages (SIP) 87

3.2.2 Mechanical Challenges
Stacked die packages pose several mechanical challenges that can affect product perfor-
mance and reliability. First is the relationship between die thickness and die size. Since
there are several chip designs for stacking various types of random access memory (RAM),
the die size and pad ring must be selected that best match the product requirements.
Chip thickness in advanced stacked die configurations are currently at 75 micrometers (μm)
for stacks up to seven dies or more. When stacking thin dies in a wire bonded package,
particular attention has to be paid to the bonded and nonbonded sides of the overhang, since
the wire bonding process imposes significant force on the die during manufacturing. A
stacked die at 75 μm usually has little to no overhang to avoid the die cracking during the
wire bonding process, whereas an overhang up to 2 mm or more can be achieved when the
thickness is allowed to increase to 150 μm or greater.
Silicon functionality and transistor performance can also be adversely affected in thin-
die situations in stacked packages if the stack, overhang, and material selection are not
chosen carefully. Because of the piezoresistive effects of silicon, assembly-induced stress
can adversely affect device performance. TCE mismatch between silicon, substrates, mold
compound, and die attach adhesive produce additional thermomechanical stresses. In
particular, spacer and adhesive materials play a large role in the total stress applied to the
silicon. In addition, these packaging materials are all polymers with widely different
mechanical properties (modulus and TCE) below and above their glass transition
temperatures. Reducing packaging-induced stress involves, therefore, a proper selection
of material properties and processing steps. Evaluating the stress is typically done through
device performance after packaging or through up-front finite element models. Finite
element models are capable of evaluating the residual stresses generated due to the
complex assembly process but need to be validated in each case. Validation is performed
through package warpage and in-plane measurements such as Moire interferometry
techniques.
Solder joint reliability (SJR) is also an area of great concern in die and package
stacking applications. Material selection for solder joints, solder joint design, intermetallic
compounds formation, overmold materials, and the substrate core material all play a
role in joint fatigue life. A TCE mismatch between the IC and package as well as between
the package and board drives the fatigue shear strain in the solder joints. Two competing
factors that determine the worst joint reliability are the global TCE mismatch driven by
the distance from neutral point (DNP) effect and the local TCE mismatch between the
package and the substrate. The ballout pattern and the die sizes are very critical for
identifying the worst joints for failure under temperature cycling. Die size and local
TCE mismatch are the primary drivers in perimeter array logic packages. For memory
packages, the ballout patterns are typically smaller than logic packages since the DNP
as the main driver for solder joint fatigue is small. In addition to this, the mold cap
height is also an important parameter for thin flexible substrates. The move from
eutectic Sn-Pb solder to lead-free Sn-Ag-Cu solder will enhance the temperature cycle
performance of the package due to the lead-free solder’s better creep properties. An
example of a typical shear-driven package-level failure of solder during the temperature
cycle is shown in Figure 3.5.
In cyclic bend and drop conditions, the package stiffness plays an important role. A
stiffer package results in more forces being transmitted to the solder ball, resulting in
faster failure. At high strain rates typically experienced in drop conditions, a much
stiffer lead-free solder results in earlier failures than leaded. Compliance of the solder