Page 138 - System on Package_ Miniaturization of the Entire System

Stacked ICs and Packages (SIP) 113

bonded onto PCB, providing the electrical interconnection of stacked chips on PCB
pads. Figure 3.38b shows, on the other hand, that chips are first mounted on both
surfaces of a lead frame by using TAB and then these lead frames are bonded together,
so that the chip stacking structure is finally established.
However, the use of TAB technology for chip stacking has been limited due to a
variety of concerns that include increased package size with large I/Os, long
interconnection lengths, relatively little TAB production infrastructure, and additional
wafer processing steps required for bumping to accommodate TAB.

3.3.3 Package Stacking
While chip stacking provides many advantages such as a small form factor, high
performance, and low cost, it has several challenges including lack of chip testability
before stacking, lower stacking process yield, and difficulty in integrating dissimilar
chips. By employing package stacking technologies, many of these issues can be
addressed, as the individual chips are prepackaged, sourced, tested, and yielded
separately and then combined once they are known to be good. Package stacking can be
realized in many different ways such as package-on-package (PoP), package-in-package
(PiP), and folded-stacked chip-scale package (FSCSP).

Package-on-Package (PoP)
PoP consists of individual packaged dies, in which a top package is stacked directly
over an existing package. Figure 3.39 shows one of the earliest versions of PoP stacking.
In this example, the PoP interconnections are realized by side terminations, similar to
chip stacking. At the sidewall of stacked packages, conductive epoxy is applied in
Figure 3.39a [43] and metal traces are formed in Figure 3.39b [44].
However, more recent types of PoP stacking structures are more like that shown in
Figure 3.40. Stacked packages are connected typically with solder balls providing both
clearance and electrical connection. This PoP stacking has been considered a major
breakthrough in the package design of mobile applications (Figure 3.41). In a typical
PoP, the top package is a multichip package that stacks flash memories and xRAM,
while the bottom package is a single-chip package, typically with a logic chip. On the
front side of the bottom package, there are land-pads, which are used for electrical
communication between the top and bottom packages by mounting the top package on
them. The height of the solder balls is adjusted to effectively encompass the logic die
and its wire bond loop height.
Figure 3.42 shows the variations of PoP stacking. Figure 3.42a demonstrates PoP
stacking realized by very short interconnects. Solder balls for package-to-package
interconnections are embedded into the substrate, and chip pads are directly connected to
substrate traces by electroplating, often referred to as bumpless interconnects [46]. In
Figure 3.42b, chips are molded by polymer materials and electric signals are routed through
holes in the molding from the front side of the chips to the back side of the molding. These
molded packages are then stacked one on top of the other with solder balls, which allow
area array interconnection in PoP [47]. Figure 3.42c shows the modernized PoP with side-
metallized interconnections. This packaging uses thin flex film as interposers, and Ni-Au
metal traces are patterned by laser etching at the sidewall of the stacked package [48].
A beneficial feature of the PoP stacking is that each individual package can be tested
as a ball grid array (BGA) package before it is stacked. In other words, the known good
package is ready for the final assembly, leading to yield improvement. This stacking