Page 148 - System on Package_ Miniaturization of the Entire System

Stacked ICs and Packages (SIP) 123

Sensor chip

MEMS RF IC MMIC

Analog LSI
Power IC Control IC

Logic IC
Flash memory

DRAM

Cache SRAM

CPU

Interposer

FIGURE 3.51 Heterogeneous integration by 3D TSV technology. (Courtesy: Zycube.)

Characteristics TSV Wire Bonding
Interconnection Interconnections can be area- Only peripheral interconnect
arrangement array or peripheral
Interconnection Shorter interconnections Much longer interconnect
length length
Electrical parasitics Much lower electrical Higher parasitics
parasitics
I/O density Potentially high density Lower I/O density
achievable
Reliability Higher reliability Less reliable

Processing IC fabrication process Packaging process

TABLE 3.3 Comparison between TSV and Wire Bonding