Page 162 - System on Package_ Miniaturization of the Entire System

Stacked ICs and Packages (SIP) 137

then grown with electroless deposition to form the wafer-to-wafer contact pads in
step 10. Alternatively, the dielectric can also be removed to form these wafer-to-wafer
contacts. In the next step, the wafers are aligned and bonded by Cu-Cu thermal diffusion
bonding. The base Si layer on the top wafer is thinned by CMP and grinding. Chemical
etching is used to remove another 1 μm of the Si layer (step 12). A layer of oxide is
deposited by plasma-enhanced chemical vapor deposition (PECVD) on the back side of
the thinned wafer to avoid Si contamination while integrating the next wafer on top of
this stack (step 13). In step 14, the oxide layer is again etched (like in step 2) to form the
trenches for depositing the copper connection. In the last step, the copper pad is formed
for connecting the next wafer on top of the stack.
Via-First Process 2
This process used by ASET, Fraunhofer, IMEC, and others is also a via-first approach like
the previous one. The difference is that the wafer bonding is carried out after thinning
the wafer, unlike in the previous approach in which these steps are carried out in the
reverse manner. The ASET process flow [88] is described in Figure 3.69, which also shows
the cross-sectional schematic of the stacked structure developed by this process.
The vias are filled with copper by electroplating. CMP is used for polishing. The
wafers are bonded either by using gold bumps or by Cu-Sn eutectic bonds. A similar
method used by IMEC is shown in Figure 3.70.
The TSVs are drilled using an ICP-RIE Bosch process. The vias are filled with Cu
using a modified Cu/ILD damascene process. Standard front-end-of-the-line (FEOL)
and back-end-of-the-line (BEOL) processes are used. The wafers are handled with a
wafer carrier. The wafers are bonded by Cu-Cu direct bonding.
Via-Last Process 1
In this example of a via-last approach of 3D integration using TSVs, RPI and IBM in
collaboration with the University at Albany have developed this SOI-based process
[83], as shown Figure 3.71 with a simplified process flow.
The wafers (with active devices and BEOL interconnects) are first precisely aligned
and bonded using polymeric adhesives such as BCB. This face-to-face initial wafer
bonding step eliminates the need for a “handle” wafer. The polymeric bonding is
tolerant to the presence of contaminants at the wafer surface. One of the wafers is
thinned down to the etch-stop region by back-side grinding, CMP, and wet etching.
Thereafter, high-aspect-ratio vias are drilled in the wafer stack. A barrier layer is
deposited before filling the vias with Cu. Another wafer can be added on top of this
stack by following similar alignment, bonding, thinning, and via formation steps.
Via-Last Process 2
This is another variation of the via-last process. The difference from the previous
approach is that the wafers are first thinned and then bonded, unlike in the previous
case where it is done the other way around. The RTI process using this approach is
used for stacking thin IC layers [89]. All the 3D processing steps are performed under
250°C. This approach can be used for either die-to-die or die-to-wafer stacking. Figure 3.72
shows the key process steps in the 3D integration process by the via-last process.
The wafer (marked as “IC2”) is bonded on a “handle” carrier substrate. It is thinned
using back-side grinding and CMP. The individual dies of the IC2 wafer are diced
(while still bonded to the carrier substrate). The individual dies of IC2 are carefully
aligned and bonded with the IC1 wafer. High-aspect-ratio vias are etched through IC2.