Page 269 - Sami Franssila Introduction to Microfabrication

248 Introduction to Microfabrication

wafers differs from n-doped wafers because some iron is unusual. This densification is seen as etch rate and pol-
held immobile by Fe-B pairs. Contamination is strongly ish rate reduction. There is room for high temperature
oxide-thickness dependent, and the pre-oxidation clean- annealed (PE)CVD oxides because thermal oxide thick-
ing strategy must be designed accordingly. Use of ultra- nesses are limited by the diffusion-controlled parabolic
high purity chemicals in a 20 nm gate oxide process growth law, whereas (PE)CVD film thickness increases
is financial waste but an absolute must in a sub-10 nm linearly with deposition time. PECVD deposition of
oxide process. 2 µm thick film plus annealing can be completed in
Photoresist developers are hydroxides, and NaOH- ca. two hours, whereas thermal oxidation would require
based developers were once the mainstay, also in two days. Thick oxides (>1 µm) are needed as mask
MOS-fabs, but organic developers such as TMAH do oxides in MEMS and in optical devices as waveg-
not pose alkali contamination risks. MEMS fabrication uides.
with KOH etching tends to be strictly separated from Deposited films may need stoichiometry tailoring,
all MOS activities. If MEMS fabrication is done in and for oxide films, oxygen anneal can result in more
a MOS fab/lab, TMAH etchant is used to eliminate stoichiometric films. Sputter and MOCVD deposited
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alkali ion contamination risk. However, TMAH and Ta 2 O 5 films are often annealed at 700 C in oxygen.
KOH etching processes are similar only in their gross This causes crystallization and oxygen deficiency is
features, and all details of rates, selectivities and etch compensated. Dielectric constant of amorphous Ta 2 O 5
stop properties need to be redone, as discussed in is ca. 25, whereas crystalline Ta 2 O 5 has ε of ca. 35.
Chapter 21. Annealing will crystallize amorphous LPCVD silicon
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Wet cleaning baths must also be dedicated to certain into polycrystalline silicon at ca. 600 C. This polycrys-
processes only. Pre-gate cleaning is very critical, and talline film is not identical to the film which has been
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only wafers that are very clean to begin with can deposited at 600 C and which is polycrystalline to begin
be processed in pre-gate cleaning baths. Gate oxide with: its grain size and grain size distribution are differ-
usually has an oxidation tube of its own; not shared ent, its surface morphology and stress state are different.
even with other front-end oxidation processes. Wet When those films are doped, they will end up with
etching baths may additionally be divided by no- different resistivities, because dopant diffusion in a poly-
resist/resist division. For example, of two HF-baths one crystalline film is dependent on grain size and grain size
is used for sacrificial oxide removal and the other for distribution. Diffusion in polycrystalline films is mainly
pattern etching. along the grain boundaries, with a minor contribution
from bulk diffusion inside grains. Diffusion of dopants
in polysilicon is, therefore, much faster than diffusion
24.6 THERMAL PROCESSES in single-crystalline silicon.
24.6.1 Film modification
24.6.2 Surface modification
Metal films have limitations both because of presence
of metal/silicon interfaces, and because the top surface Silicon nitride is the standard masking material for
can oxidize. Sputtering, evaporation and electrochemical localized thermal oxidation of silicon (LOCOS). The
deposition are basically room temperature processes, and surface of nitride will react with oxygen, even though
even mild thermal treatments, at and below 400 C can oxygen cannot diffuse through the nitride. This modified
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modify film properties dramatically. Electroless copper surface layer is termed oxynitride. Its thickness is limited
can have resistivity of 4 µohm-cm as-deposited, but to a few nanometres. Somewhat similar, extremely
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400 C anneal in N 2 /H 2 can bring it down to 2 µohm-cm. etch-resistant material can be deposited by PECVD,
This results from grain growth and void annihilation. using a process that has features of both oxide and
Grain growth is proportional to square root of anneal nitride deposition.
time, indicative of a diffusion limited process (cf. Nitridation in molecular nitrogen can sometimes take
thermal oxidation). place, even though N 2 is usually regarded as an inert
CVD films (and PECVD films in particular) and spin gas and often employed in place of argon. When wafers
coated films are often porous and unstable. PECVD films are loaded into oxidation furnace, nitrogen is used as
may contain up to 30 at. % hydrogen, which will diffuse a curtain gas and some nitridation of silicon surface is
during subsequent processing. Inert anneal at 900 C possible because the temperatures are fairly high.
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will densify (PE)CVD oxide film into more thermal Intentional nitridation is usually done with ammo-
oxide –like state. Thickness reduction of 10% is not nia. Oxide can be nitrided in NH 3 . Oxynitride film