Page 301 - Sami Franssila Introduction to Microfabrication

280 Introduction to Microfabrication

(a) (b) (c)
Figure 27.6 Damascene process: (a) trenches etched in oxide till underlying metal; (b) metal overplating into oxide
trenches and (c) metal CMP

(a) (b) (c)
Figure 27.7 Dual damascene metallization: (a) two lithography and two etching steps define vias and wires in oxide;
(b) vias and wire trenches filled by metal in one deposition step and (c) metal polishing to yield a planar surface

27.2.2 Stacked vias as residues from processing can accumulate in these
pockets. It must be remembered that even though CMP
When vias can be stacked on top of each other in a multi- can planarize, the sixth level can never be as smooth as
level metallization scheme, a lot of area can be saved and the first level.
freedom of wire routing increases. In Chapter 24, sput-
tering step coverage was found to be poor for stacked
vias (Figure 24.12), but with W-plugs and planarization, 27.3.1 Dual damascene
stacking becomes natural. In Figure 27.5, tungsten plugs
can be seen on top of each other. Misalignment is still One of the advantages of damascene metallization
there, but because the surfaces are planar, misalignment is its ability to offer even more ingenious multi-
does not lead to topography build-up. level metal fabrication routes. Dual damascene process
(Figure 27.7) combines via filling and wire metal depo-
sition into one integrated process step.
In practice, it has been difficult to decide the
27.3 DAMASCENE METALLIZATION
order of process steps: how should lithography and
etching of vias and wire trenches actually be combined
Damascene metallization (Figure 27.6) relies on etching
trenches in oxide, filling those trenches with metal, for maximum benefit. Dual damascene promises great
and CMP for removal of excess metal. As we have reductions in the number of process steps, but it is not
seen in Figure 16.1, this will result in a structure an easy process. Dual damascene discussion continues
identical to the one made by metal deposition, metal in connection with copper/low-k materials towards the
end of this chapter.
etching and oxide planarization. Oxide etching, which
is easy, and copper CMP, which is difficult, are used
in damascene. Because copper etching is practically
27.4 METALLIZATION SCALING
impossible, copper metallization must be implemented
in damascene. In CMOS front-end scaling, vertical parameters: junction
The CMP can provide globally planar surface, depth x j and oxide thickness t ox are scaled to smaller
but if the original topography is not amenable to and smaller values, leading to improved transistor
global planarity, CMP cannot help. If the deposition performance. In the backend, however, vertical scaling
process leaves voids (Figure 7.17), these can emerge as is detrimental. If metal lines are made thinner, resistance
crevasses after the CMP. This poses reliability problems increases and linewidth scaling works in the same