Page 247 - A Practical Guide from Design Planning to Manufacturing

Circuit Design 219

W
Clock

Data Out Open when clock high

N-latch

W
Clock

Data Out Open when clock low

P-latch
Figure 7-18 N-latch and P-latch.

When a latch is open, new data flows directly through to the output,
but when the clock changes and the latch closes, it will catch whatever
data is there at the time and hold it until the latch opens again. New
data arriving while the latch is closed must wait for the clock signal to
change before it can pass through.
Latches are called sequentials because not only do they retain previously
captured values, they also enforce a sequence between the different data
signals. In a pipelined processor, the data from multiple different instruc-
tions is flowing through the processor circuits at the same time. Because
some paths through the circuits are faster than others, it is possible for
later issued instructions to overtake instructions issued earlier. If this
were to happen, it would be impossible to distinguish the correct data for
each instruction. Sequentials prevent this by enforcing a separation in
time between the data of different instructions. Chapter 6 discussed how
flip-flops are commonly used to separate the pipestages of a pipelined
processor. A circuit implementation of a flip-flop can be created by com-
bining two latches.
The flip-flop shown in Fig. 7-19 is a P-latch immediately followed by
an N-latch. When the clock is low, the P-latch will be open but the N-latch
will be closed. When the clock is high, the P-latch will be closed but the
N-latch will be open. There is never a time when both latches are open
at the same time. This means the clock signal must go low and then go