Page 1110 - The Mechatronics Handbook

41

Synchronous and

Asynchronous

Sequential Systems

41.1 Overview and Definitions
Synchronous Sequential Systems • Flip-Flops and
Latches • Mealy and Moore Models • Pulsed and Level Type
Inputs • State Diagrams
41.2 Synchronous Sequential System Synthesis
Design Steps
41.3 Asynchronous Sequential System Synthesis
Design Steps
Sami A. Al-Arian 41.4 Design of Controllers’ Circuits and Datapaths
University of South Florida 41.5 Concluding Remarks

41.1 Overview and Definitions

Traditionally, digital systems have been classified into two general classes of circuits: combinational and
sequential systems. Combinational systems are logic circuits in which outputs are determined by the
present values of inputs. On the other hand, sequential systems represent the class of circuits in which
the outputs depend not only on the present value of the inputs, but also on the past behavior of the
circuit. In most systems a clock signal is used to control the operation of a sequential logic. Such a system
is called a synchronous sequential circuit. When no clock signal is used, the system is referred to as
asynchronous.

Synchronous Sequential Systems
Figure 41.1 shows the general structure of a synchronous sequential system. The circuit has a set of
primary inputs X and produces a set of primary outputs Z . In addition, it has sets of secondary inputs
and outputs, Q + and , respectively. These sets of signals are inputs and outputs to state (or memory)
Q
elements or devices called flip-flops (FFs) or latches. The outputs of these devices constitute the present
Q
states , while the inputs constitute the next states or Q + . There are several types of such devices, as well
as many variations of these types, namely, set-reset (SR), delay (D), trigger (T), and JK (a combination
of SR and T) FFs and latches. Table 41.1 shows the behavior of each of these types.

Flip-Flops and Latches
The outputs of the FFs or latches, which are sequential devices, are determined by the present values of their
inputs as well as the values of their present states. However, FFs are edge-triggered devices, meaning that
state transitions might take place only during one clock cycle. This clock transition is either positive edge

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